1. Field of the Invention
The present invention relates to floating point compare operations. More particularly, the present invention provides a method and apparatus for performing a floating-point compare operation which is significantly faster than in the prior art, and which requires less hardware to implement.
2. Description of the Related Art
Increasing demands for faster computers make it necessary to continually explore new ways to improve the efficiency of operations so that operations are performed as quickly as possible using the least amount of hardware resources such as time, space, etc.
FIG. 1 is a block diagram of a typical prior art central processing unit (CPU) in a computer. Referring to FIG. 1, CPU 10 includes a prefetch and dispatch unit 12, an integer execution unit 14, a floating point unit 16, a memory management unit 18, a load store unit 20, an external cache unit 22, and a memory interface unit 24.
Mathematical operations are typically performed either by the integer execution unit 14 or the floating point unit 16, depending on the type of data being operated on. The present invention is specifically directed at comparing two floating point numbers to determine whether a first floating point number is greater than or equal to the second floating point number, or alternatively whether the first floating point number is less than the second floating point number.
In prior art CPU""s, when comparing two floating point numbers, the mantissa and exponent for each of the two numbers are compared separately in different adders. The compare results for each of the mantissa and exponent compares are then combined with sign logic to generate a final comparison result. While prior art methods are suitable for their intended purposes, they require hardware that is complex and slow.
It would therefore be beneficial to provide an apparatus and method for performing floating point compare operations using methods that are performed more quickly than the prior art, and using an apparatus which is less complex than required in the prior art.
Floating-point numbers are typically represented in sections of bits. By way of example a sign of a floating-point number is represented in a sign bit that is the left most bit (most significant bit (MSB)). A xe2x80x9c0xe2x80x9d value in the sign bit typically represents a positive number and a xe2x80x9c1xe2x80x9d in the sign bit typically represents a negative number.
The center section of the binary representation of a floating-point number is the mantissa section of the floating-point number. The bits in the mantissa section represent the value or magnitude of the floating-point number, expressed in binary. The mantissa section can be as many bits as are necessary to represent the value or magnitude of the floating-point number.
The right section of the binary representation of a floating-point number is the exponent section of the floating-point number. The bits in the exponent section represent the value or magnitude of the exponent of the floating-point number expressed in binary.
Each of the sections of the digital representation of the floating-point number can have as many bits as necessary. Further, the sections can be different bytes. By way of example, a left most byte (8 bits) can be allocated to the sign bit function. One or more bytes can be allocated to each of the mantissa and exponent sections.
Broadly speaking, the present invention fills these needs by providing a system, method and apparatus for performing a floating point compare operation. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment, a method for comparing two floating point numbers is described, the method includes determining if a first number is less than a second number or alternatively if the first number is greater than or equal to the second number. The method also includes extending the sign bit for each number, subtracting the second number from the first, and inverting the sign bit of the result of the subtraction operation if the sign bits for the first and second numbers are both ones. Finally, the sign bit of the subtraction result is checked to determine whether it is a one. If yes, the first number is less than the second. If no, the first number is greater than or equal to the second.
In one embodiment, a system and method for comparing two floating-point binary numbers includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.
In one embodiment, the first and second floating point binary numbers to be compared are in the form of a sign bit as a most significant bit and a magnitude in the remaining bits.
In one embodiment, subtracting the second sign extended number from the first sign extended number to determine a subtraction result can include determining a two""s complement of the second sign extended number and adding the two""s complement of the second sign extended number to the first sign extended number.
The subtraction result can further include truncating the subtraction result if the sign bit of the first number is equal to the sign bit of the second number and the subtraction result included an overflow bit. The truncated subtraction result is equal to the subtraction result having the overflow bit truncated.